1. Field of the Invention
This invention relates to avalanche photodiodes (APD's) used in optical communication systems and more specifically to a single chip ASIC and compact packaging solution for an APD and its bias and temperature compensation circuits.
2. Description of the Related Art
PIN photodiodes and avalanche photodiodes (APDs) are both used as detectors in fiber optics communications systems. Standard PIN photodiodes combined with a TransImpedance Amplifier (TIA) to boost the low level signal from the PIN diode are available in compact packages and can be fully interfaced via 4 I/O pins; power supply, ground and a differential output. An industry standard package is the 4-pin TO-46 package or “can”, which is compact, BellCor qualified and designed into many optical applications. The 4-pin TO-46 can has differential output pins DATA and DATA−, power supply pin Vs and ground pin GND. The term “pin” as used herein is intended to mean any electro-mechanical package I/O, which is commonly referred to as pins, pads or contacts.
A standard APD increases receiver sensitivity compared to an identical receiver using a PIN diode by 8 to 10 dB of optical power depending on details of the amplifier design, bit rate, etc. This enhancement of sensitivity, however, is achieved at the expense of having to provide a high voltage bias circuit that accurately controls a bias voltage (VAPD) of the APD, which is complicated by the fact that the APD gain and therefore the reverse bias requirement is temperature dependent.
The gain of a typical n+pπp+ APD at a given temperature increases rapidly with increasing reverse bias at low voltages corresponding to a sweepout of the device and then increases more gradually until avalanche breakdown is approached where the gain also increases very rapidly. If the temperature of the device is increased, the gain for a given bias voltage decreases because of the negative temperature dependence of the ionization coefficients for holes and electrons. To maintain appropriate gain and optimum reverse bias as a function of temperature, the bias circuit must vary the bias voltage of the device in a controlled manner. Failure to do so can cause the APD to be driven further into breakdown where it becomes exceedingly noisy, thereby drastically reducing the signal to noise ratio of the system.
As shown in FIG. 1, a typical APD and bias circuit solution includes an APD 10, a transimpedance amplifier (TIA) 12 and a pair of capacitors C1 and C3 inside a 5-pin package 14 such as a TO-46 package. 5-pin APD packages are available from Sumitomo (F0852491T APD Preamplifier Module), Mitsubishi, NEC, and others. The addition of the fifth pin increases the complexity of the package itself and the mechanical design of the board on which it is mounted.
The 5-pin TO-46 package has a power supply pin Vs, a ground pin GND, differential output pins DATA and DATA− and an APD voltage pin VAPD, which receives the bias voltage from an external high-voltage bias generator 18. A temperature sensor 20, which can be co-located inside the can with APD 10 or outside the can as long as the sensor remains in thermal contact with the APD, monitors the temperature of the APD. A temperature compensation circuit 22 determines what adjustments must be made to the bias voltage to maintain the appropriate gain and optimum bias voltage and controls bias generator 18 accordingly. An interface controller 24 sends APD temperature correction coefficients to the temperature compensation circuit 22. Interface controller 24 also sends requests for APD temperature and received power data to bias controller 18 and receives responses to these requests from bias generator 18 and temperature compensation circuit 22 via interfaces 26 and 28, either serially or in parallel. Typically these serial or parallel interfaces are 1-8 lines each and interface controller 24 communicates the same information with the rest of the network over an I2C serial connection 30. Interface controller 24 typically includes an EEPROM plus serial identification feature, which is mandated by industry multi-sourcing agreements covering GBIC and small form factor transceivers and allows the network to readout information about the transceiver and its status.
A number of companies including Lucent Technologies (Low-Cost, High-Voltage APD Bias Circuit with Temperature Compensation, Application Note January 1999), Fairchild Semiconductor (ILC 6380/81 SOT-89 Step-up Dual-Mode Switcher with Shutdown), and Maxim (28V Internal Switch LCD Bias Supply in SOT23) provide chip sets for the external bias generator 18 (temperature compensation circuit 22 is typically provided by the customer). As shown in FIG. 2 and as is typical of these chip sets, bias generator 18 includes an integrated circuit (IC) 32 that provides the Pulse Width Modulation (PWM) functions and external electronic components including inductor L1, FET Q1 and diode D1 that convert the low input supply voltage, typically in the range of 3.3-5VDC to a high APD bias voltage, typically in the range of 40-70VDC via the flyback effect. The high voltage is generated when the FET Q1, acting as a switch is cycled from “ON” to “OFF” by turning off its gate drive voltage. The current through inductor L1 changes instantaneously, causing a high transient voltage proportional to L(di/dt), which is rectified by diode D1 and stored by charge storage capacitor C2. As successive cycles of FET Q1 are completed, charge is built up on storage capacitor C2 and a limited amount of current may be supplied at a higher voltage, VAPD. The circuit uses a feedback connection from the VAPD output to control the duty cycle of the pulses via the PWM circuit, thus controlling and regulating the VAPD output. Although PWM voltage control is preferred, Pulse Frequency Modulation and other schemes involving feedback and proportional control may be used to control the output voltage of the APD bias supply.
IC 32 is fabricated using a low voltage process, e.g. less than 30V typically. Using the buck/boost converter topology, FET Q1 and diode D1 are both exposed to high voltages in excess of 30V and cannot be integrated onto the IC chip. Furthermore, the companies design the general-purpose bias generators to maximize power efficiency as they are used in a wide variety of applications including cell phones, pagers, and displays. To maximize power efficiency, PWM controllers are rarely switched at frequencies higher than 500 KHz and typically about 300 KHz. As a result, the passive components (inductors and capacitors) are large. The lack of integration into a single IC chip and the size of the passive components necessitate placement of the bias generator outside the APD package and provisioning of the bias voltage via the fifth pin. Instead of the buck/boost inductor coupled approach, other topologies for the DC-DC converter may be used such as a transformer coupled circuit.
As also shown in FIG. 2, a typical customer added temperature sensor and compensation circuit includes a thermistor RT in thermal contact with APD 10 and resistors R2, R3 and R4 that adjust the bias voltage with fluctuations in temperature. Again these passives are external to the APD package. The output voltage is set according to VAPD=VREF ×((R1+Reff)/Reff) where VAPD is the APD voltage, VREF is the internal reference voltage at the feedback comparator input (FB), and Reff is the effective resistance of the compensation circuit (R2+R3)+R4||RT.
The current state of the art is to use external bias and temperature compensation circuits in combination with a 5-pin APD package. The multi-chip approach simplifies design; each chip is optimized independently, simplifies packaging; each chip is packaged separate and simplifies control by providing multiple pins for control of the bias and temperature circuits via a standard serial interface. However, the external bias and temperature circuits occupy valuable space on the optical transceiver PC board, for example, and increase parts count, hence cost. The fifth pin also complicates the packaging of the device.
As fiber optic networks move towards CWDM application, longer transmission distances, increased network nodes, small form factor transceivers and standardization, a demand for compact and less expensive integrated APD packages is beginning to grow. The current multi-chip ASIC solution cannot scale down in either size or cost to meet this demand.